ESP Accelerators in Chisel

This project provides an Embedded Scalable Platform (ESP) Accelerator socket that can be used for writing ESP-compatible accelerators in chisel3.

A concrete ESP-compliant accelerator is composed from an esp.Implementation that aligns to an esp.Specification. The resulting accelerator is then wrapped with an esp.AcceleratorWrapper that maps the interfaces of the accelerator to the expected top-level interface. The esp.Specification is abstract in a configuration that defines metadata that the ESP framework requires.

When generating Verilog from an esp.Implementation, a FIRRTL annotation is emitted containing the accelerator configuration. A custom FIRRTL transform EmitXML will convert this configuration information to XML that the ESP framework needs.

We currently provide one example accelerator, esp.examples.CounterAccelerator that always reports as being finished a run-time configurable number of cycles in the future.

To build the example accelerator, simply run:

sbt run

To run our existing tests use:

sbt test